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Book :: Computer Organization and Architecture

Chapter 1 + 2: Introduction, Evolution and Performance Concepts

• Define Computer Organization and Computer Architecture. What is the difference between the two? (January-June 2023)
• What are the key concepts of Von Neumann architecture? Define hardware and software programming. (January-June 2023)
• Why study Computer Organization and architecture? Describe the structure and functions of a computer. (January-June 2021)
• a) What is general term, is the distinction between computer organization and computer architecture. List and briefly define the main structural components of a computer. b) Explain Moore’s Law. On the IAS, describe the process that the CPU must undertake to read a value from memory and to write a value to memory… (January-June 2021)
• Describe the evolution of DRAM and processor characteristics. (January-June 2021)
• Give the learning outcomes from this course with respect to your current and forthcoming professional perspective. (Session 2019-2020)
• a) What is computer family? b) Find out the quotient and reminder… d) Enlist the categories of computer’s functions… (Session 2019-2020)
• a) Give the technological features for switching computer generation. Also mention the key technological development for any 2 successive generation transition. (Session 2019-2020)
• Mention the characteristics of computer family. Distinguish among sequential, nested, time-sequence and priority interrupt. (January-June 2020)
• Enlist the processors from 4 bit to 64 bit. Mention the categories of IAS instruction set with example… (January-June 2020)
• a) Why do you need to study computer organization and architecture? b) A hypothetical machine has 3-bit opcodes. (January-June 2018 Final)
• a) Enlist the registers of IAS computer with its functionality. b) What are the difference among sequential, direct, and random access? c) Describe about set associative mapping… (January-June 2018 Final)
• What is computer system. Distinguish between synchronous and asynchronous timing bus operation. (part of a multi-question block, January-June 2018 Final)
• b. Distinguish between computer architecture and organization. Discuss the general roles of processor. c. What does the computer generation with its key trending technologies? d. Why study the computer organization and architecture? (January-June 2018 Midterm)
• [1.A] Explain about the learning outcomes for studying the Computer Organization and Architecture course. (2016-2017)
• [1.B] Illustrate the basic elements of a digital computer. (2016-2017)
• [C.II] Mention the concept of von Neumann architecture. (Year Not Explicitly Stated)
• Four benchmark programs are executed on three Laptops with the following results: (Question incomplete) (2016-2017)

Chapter 3: A Top-Level View of Computer Function and Interconnection

• Define Interrupts. What are the approaches for handling multiple interrupts? Illustrate and explain. (January-June 2023)
• Give the basic elements to design different buses. Describe PCI bus structure. (January-June 2022)
• Define interrupts. How do the multiple interrupts managed? (January-June 2022)
• Give the elements for designing bus. (January-June 2021)
• If “a large number of device are connected to the buses, performance will suffer”- explain this statement. (part of a multi-question block, January-June 2021)
• Distinguish among local bus, system bus and expansion bus. (January-June 2021)
• Mention the basic elements to design different buses. Describe PCI bus structure. (January-June 2020)
• b) Define interrupts. How does the processor handle multiple interrupts? (January-June 2018 Final)
• c. Define interrupts. How does the processor handle multiple interrupts? (part of a multi-question block, January-June 2018 Midterm)
• When interconnection is needed in computer? Briefly describe the considering elements to design a bus. (January-June 2017)
• [D.] Justify the statement “More dedicated interconnection produce faster computer”. (Year Not Explicitly Stated)
• Differentiate between system bus and local bus. (Year Not Explicitly Stated)

Chapter 4: Cache Memory

• Define access time and cycle time. (January-June 2023)

• Distinguish among sequential, direct and random memory access. (January-June 2023)

• a) How can you characterize the memory of your computer? b) Explain Booth’s algorithm… c) What is computer system… (January-June 2018 Final)

• [B.1] What is the general relationship among access time, memory cost, and capacity? (Year Not Explicitly Stated)

• Consider a machine with a byte addressable main memory of $2^{16}$ bytes and block size of 8 bytes. Assume that a direct mapped cache consisting of 32 lines is used with this machine. (Includes tag/line/byte division, address mapping, bytes stored together, and total cache size) (January-June 2023)

• Consider a machine with a byte addressable main memory of $2^{16}$ bytes and block size of 8 bytes. Assume that direct mapped cache… (Includes tag/line/byte division, address mapping, total cache size, and purpose of tag) (January-June 2022)

• a) Describe about set associative mapping. Give the replacement algorithms in cache memory. b) Briefly explain the working mechanism of operating system… c) Find out the quotient and reminder… d) Define random access memory… (January-June 2021)

• Consider a machine with a byte addressable main memory of $2^{16}$ bytes and block size of 8 bytes. Assume that direct mapped cache… (Includes tag/line/byte division, address mapping, and total cache size) (January-June 2021)

• a) Distinguish among direct, associative and set associative mapping of cache. b) …Tag, Line and Word… c) Explain different replacement algorithms… d) …DRAM and SRAM… e) …EPROM, EEPROM. (Session 2019-2020)

• a) Give the replacement algorithms in cache memory. b) Distinguish between SRAM and DRAM. If an instruction contains four addresses… c) Explain error detection and error correction… (January-June 2018 Final)

• Describe about set associative mapping. Suppose FFFFF8 is an address of 16M memory. Find out the corresponding address of 16K line size of set associative mapping. (part of a multi-question block, January-June 2018 Final)

• Consider a machine with a byte addressable main memory of $2^{16}$ bytes and block size of 8 bytes. Assume that a direct mapped cache… (January-June 2018 Midterm)

• Consider a machine with a byte addressable main memory of $2^{16}$ bytes and block size of 8 bytes. Assume that a direct mapped cache… (Includes tag/line/byte division, address mapping, bytes stored together, and purpose of tag) (January-June 2017)

• What is the basic elements of Cache Design? (2016-2017)

• [B.3] Explain Direct-Mapping Cache Organization with diagram. (Year Not Explicitly Stated)

Chapter 5: Internal Memory

• Mention the characteristics of semiconductor memories (4 types). (part of a multi-question block, January-June 2023)

• Why RAM is so called? (January-June 2022)

• Prepare a question on semiconductor main memory and answer it yourself? (January-June 2021)

• a) Describe RAM working mechanism. b) If “a large number of device are connected to the buses…” (January-June 2021)

• What are the key properties of semiconductor memory? What is the difference between DRAM and SRAM… (part of a multi-question block, January-June 2021)

• Define memory cell. Describe the structure of typical Memory Cell. (part of a multi-question block, January-June 2021)

• a) What is chip logic? Describe a 16 Megabit DRAM ($4M\times 4$) memory structure. b) How Error-Correcting Code works? Describe the Hamming Error-Correcting Code Procedure… (January-June 2021)

• Why RAM is so called? (January-June 2018 Midterm)

• Distinguish between SRAM and DRAM. (January-June 2018 Midterm)

• [B.4] Distinguish between DRAM and SRAM in terms of characteristics such as application speed, size, and cost. (Year Not Explicitly Stated)

• Describe the structure of SRAM. Give the features of SRAM and DRAM. (Year Not Explicitly Stated)

Chapter 6: External Memory

• Explain RAID 5. (January-June 2023)
• a) What is RAID? Explain error detection and error correction mechanisms in semiconductor memory. b) Give the technological features of the storage: CD, DVD, HDD, SSD, flash. c) Why input/output module… d) What is interrupt?… (Session 2019-2020)
• Explain the features of RAID. On RAID 5, what is strip size and coefficient for branch instruction. Explain the operation used to deal the branches in pipeline. (January-June 2018 Midterm)
• [1.D] How are data read from a magnetic disk? (2016-2017)
• [2.A] … i) What is the disk capacity? ii) What is the average access time? … iii) Estimate the time to read/transfer a 5MB file. iv) What is the burst transfer rate? (2016-2017)

Chapter 7: Input/Output

• What is an I/O module, and why is it necessary? (January-June 2023)
• In this case, the 12-bit address identifies a particular I/O device. Show the program execution steps… i. Load AC from device 99. ii. Add contents of memory location 555 iii. Store AC to memory location 666. (January-June 2023)
• Consider a hypothetical microprocessor generating a 16-bit address… (Includes memory/I/O space, and port number questions) (January-June 2021)
• a) Distinguish between program driven and interrupt driven I/O. b) ii) Assume numbers are represented in 6-bit… c) Why I/O module is used… d) Write short notes on… Dual core… (January-June 2021)
• Describe peripheral devices. (January-June 2019)
• Give the classification of peripheral devices. Explain the function of an I/O module. (part of a multi-question block, January-June 2018 Final)
• Describe peripheral devices. (January-June 2018 Midterm)
• [1.E] List and briefly define three techniques for performing I/O. (2016-2017)

Chapter 9: Computer Arithmetic

• Assume numbers are represented in 6-bit two’s complemented representation. Show calculation of the following. a) -A + B (Hex) b) -33 + 17 (Decimal) (January-June 2023)
• Calculate the multiplication operation using Booth’s algorithm for Q = -17 (multiplicand) and M = 16 (multiplier). (January-June 2023)
• Find out the quotient and reminder by performing two’s complement division operation where divisor = -3 and dividend = -7. (January-June 2021)
• Find out the quotient and reminder by performing two’s complement division operation where divisor = 4 and dividend = -7. (part of a multi-question block, Session 2019-2020)
• Find out the quotient and reminder by performing two’s complement division operation where divisor = 3 and dividend = -7. (January-June 2019)
• Explain Booth’s algorithm with flowchart. Mention steps of interrupt driven I/O. (January-June 2019)
• Explain Booth’s algorithm for multiplicand Q= -3 and multiplier M= 7. (part of a multi-question block, January-June 2018 Final)
• Explain two’s complements division procedure for dividend D=-12 and divisor M= -3. (part of a multi-question block, January-June 2018 Final)
• Assume numbers are represented in 6-bit two’s complemented representation. Show calculation of the following. (January-June 2018 Midterm)
• Find out the quotient and reminder by performing two’s complement division operation where divisor = -3 and dividend = -7. (January-June 2018 Midterm)
• Explain Booth’s algorithm with flowchart. Mention steps of interrupt driven I/O. (January-June 2018 Midterm)
• [A.] Explain hardware implementation of unsigned binary multiplication for multiplicand=13 and multiplier=11. (Year Not Explicitly Stated)
• [B.] Analyze the statement “CPU performs all arithmetic operation using addition”. (Year Not Explicitly Stated)
• [A] What is the difference between the two’s complement representation of a number and a two’s complement of a number? ii) If an instruction contains four address… (Year Not Explicitly Stated)
• [B.A] Explain two’s complement division procedure for dividend D= -7 and divisor M= -3. (Year Not Explicitly Stated)
• A given microprocessor can work on 8-bit byte. What is the smallest and largest integer… a) Unsigned b) Two’s complement (part of a multi-question block, Year Not Explicitly Stated)

Chapter 10: Instruction Sets: Characteristics and Functions

• a) Define computer instructions and describe their types. … c) What are logical, arithmetic, and cycle (rotate) shifts? Apply… to 10100110. (January-June 2023)

• “Each operation needs operand” justify this statement. Briefly describe various categories of operand. (Session 2019-2020)

• a) Which issues are responsible for designing instruction set? b) Explain two’s complements division procedure… c) Give the classification of peripheral devices… (January-June 2018 Final)

• Explain different types of operation. Perform arithmetic left shift (10100110) for 3 bits and right rotate (10100110) for 3 bits. (part of a multi-question block, January-June 2018 Final)

• What is the difference between an arithmetic shift and a logical shift? (part of a multi-question block, January-June 2021 & Session 2019-2020)

• [TD] List and explain the instruction set design issues. (Year Not Explicitly Stated)

• [B.E] Differentiate between arithmetic shift and logical shift. (Year Not Explicitly Stated)

• What is a procedure, and why is it necessary? Illustrate and explain the procedure mechanism. (part of a multi-question block, January-June 2023)

• How interpreter is used to program system? classify interpreters. (part of a multi-question block, Session 2019-2020)

Chapter 11: Instruction Sets: Addressing Modes and Formats

• Where zero-address instructions are applicable and how? Explain. (part of a multi-question block, January-June 2023)
• Explain different addressing mode. (January-June 2023)
• a) Define Register addressing. Describe Register (Instruction) format. b) What is micro-architecture?… (January-June 2021)
• Explain instruction length variation with example. Explain the issues regarding a instruction set design. (part of a multi-question block, Session 2019-2020)
• a) What do you mean by variable length addressing? Why is it necessary? b) Explain various different addressing techniques in computer programming. (January-June 2018 Final)
• Mention the advantages and disadvantages of variable length addressing. (January-June 2018 Midterm)
• [C.I.V] Define instruction format. Why does the variable length instruction format used in CPU operation? (Year Not Explicitly Stated)

Chapter 12: CPU Structure and Function

• What are the steps of the instruction cycle and the instruction “SUB B, A”… (January-June 2023)
• List and briefly define the possible states that define an instruction execution. (January-June 2021)
• What is instruction pipelining? Describe the Six Stage CPU Instruction Pipelining with timing diagram. (part of a multi-question block, January-June 2021)
• a) Describe pipelining. How can the pipeline be sustained in case of branch dealing? b) i. “Pipeline processing with 4 stages is time faster…” ii. How interpreter is used… (Session 2019-2020)
• a) What general roles are performed by processors? b) What do you mean by user visible register in CPU? Also mention advantages and disadvantages of condition codes. (January-June 2018 Final)
• a) What is the function of condition codes? … b) Describe pipelining. “Pipeline processor with 4 stages is time faster…” (January-June 2018 Final)
• Explain the detection between the states: sequence and time sequence of an operation. Illustrate and list the instruction cycle states. (January-June 2018 Midterm)
• [1.C] What are the roles of different register of control unit and the ALU? (2016-2017)
• [B.C] Explain performance and performance penalty of instruction pipelining. (Year Not Explicitly Stated)
• Assume a pipeline with 4 stages: fetch instruction (FI), decode instruction and calculate address (DA), fetch operand (FO) and execute (EX). Draw a timing diagram for… a sequence of 9 instructions… (Year Not Explicitly Stated)

Chapter 15: Control Unit Operation and Microprogrammed Control

• a) Describe about control signals of CPU. b) “Each operation needs operand”… (January-June 2018 Final)
• [B.B] Analyze the relationship between instruction and micro-operation. (Year Not Explicitly Stated)

Other Resources

EPROM

• Describe the structure of SRAM. Distinguish among PROM, EPROM, EEPROM and flash. (January-June 2022)
• Describe the structure of SRAM. Distinguish among PROM, EPROM, EEPROM and flash. (January-June 2018 Midterm)

Most probably I missed some questions and are colladed with chapter 4 :(

Direct Memory Access (DMA)

• What are the differences among Programmed I/O, Interrupt-driven I/O and direct memory access (DMA)? (January-June 2023)
• Describe with flowcharts How does a DMA module transfer control to the processor after its task? Does it interrupt the processor? (January-June 2023)
• Define cycle stealing in DMA. (January-June 2023)

Virtual Memory

• Determine the number of page table entries that are needed… (part of a multi-question block, Session 2019-2020)
• How does the page fault handle in VM system. (part of a multi-question block, Session 2019-2020)
• Explain the responsibility of memory management unit in computer system. (Year Not Explicitly Stated)
• Define virtual address and physical address space. Explain page miss mechanism in virtual memory system. (Year Not Explicitly Stated)

CISC vs RISC

• Give the features of CISC… (part of a multi-question block, January-June 2023)
• Give the characteristics of RISC and CISC. (January-June 2021)
• a) Distinguish between CISC and RISC. (Session 2019-2020)
• Distinguish between CISC and RISC. (January-June 2018 Midterm)
• [B.D] Explain RISC architecture. Differentiate between RISC and CISC. (Year Not Explicitly Stated)

MISC

• Mention the advantages and disadvantages of position codes. (Session 2019-2020)
• Give the features of… Corei7 in the perspective of computer architecture and organization. (part of a multi-question block, January-June 2023)
• Write short notes on (Any two) i) Dual core. ii) Pentium 4. iii) Core i7. (part of a multi-question block, January-June 2021)
• d. Mention data usage for multicore and give a 2-domain instruction of Intel Pentium product. (part of a multi-question block, January-June 2018 Midterm)

I think, I have made a tons of mistakes :( Sorry for the trouble…

Don’t just follow blindly, please check the question for yourself as well…